Linux software parametric technology

DAC Introductions Run the Gamut - Industry Trend or Event

All the worldas EDA players hit Los Angeles this week for the 37th annual Design Automation Conference (DAC). Hereas a sampling of what theyall be talking about:

CadMOS Intros Electrical Rule Checker

CadMOS Design Technology Inc. is introducing ArctIC, an electrical rule checker for system-on-a-chip designers. CadMOS says the tool checks for electrical integrity of complex digital, memory and mixed signal designs. ArctIC allows designers to define a set of rules, and check the design exhaustively for violations. The software also compiles a knowledge base that designers constantly add to as the design technology and practice change.

"Using ArctIC, designers can quickly isolate hook-up problems as well as identifying anomalous circuit structures that could cause functional, timing, power or yield problems," said Charlie Huang, chief executive officer of CadMOS.

The rules include both built-in checks and user-written rules. The built-in checks include checks for issues related to circuit topology such as incorrect transistor sizing, to timing such as latch writability, and noise immunity such as charge-sharing.

ArctIC is available now on Sun Microsystem's Solaris 2.6 and Hewlett-Packard's HPUX 10.20. Pricing starts at $17,000 U.S. list for an annual time-based license including maintenance. ArctIC requires a SPICE netlist and a control file in Tcl format. ArctIC also accepts interconnect parasitics, including coupling in DSPF and SPEF formats. ArctIC generates error reports in HTML format. ArctIC has an option to check noise-related problems using CadMOS' PacifIC software.

Get2Chip Synthesizing 1M-gate Designs Daily

Cadence Design Systems Inc. will be happy to know that Synopsys Inc. has another synthesis challenger. Start-up Get2Chip.com reports it will synthesize a 1 million-gate design from register transfer level (RTL) to gates in six hours every day at its DAC booth, No. 4819. Called Volare, Get2Chips' front-end tool suite "blazes through more than 3,000 gates per minute on a single-processor PC-class machine with quality of results in area and timing that are better than current tools," the firm boasts.

Volare achieves such runtimes by a patented "Global Focus Mapping" algorithm that synthesizes the entire design without requiring user partitioning or time budgeting. The synthesis engine is complemented by a topological modeling capability called Topomo that performs block-level design and wire planning. Get2Chip says Topomo is the market's first fully integrated synthesis-and-design planning technology that addresses front-end timing convergence.

Volare supports multiple design methodologies including architectural, RTL, data path and gate-level design, according to Bernd Braune, president and chief executive officer at Get2Chip.com. The platform is also well suited for intellectual property creation, reuse and exchange and will be offered stand-alone or as a Web-based service. The technology has been developed under the Linux operating system with a Java front-end, Braune said.

The Architectural Synthesis and Mega Logic modules of Volare are currently available. Topomo and a full release of the user interface will be available later this year. Some of the Volare technology is licensed from Meropa Inc. of Munich, Bavaria. The firm also has an R&D center in San Jose.

TransEDA Ups Verification Ante

TransEDA, San Jose, will release the latest version, 6.1, of its Verification Navigator design suite at DAC. Version 6.1 is said to more than double the performance of Verilog code coverage using the most common set of coverage metrics. Also, a new test suite optimization engine called VN-Optimize increases capacity by more than 100 times, enabling reduced simulation time for large regression test suites. Verification Navigator 6.1 will be available this month starting at $20,000. Existing customers currently under maintenance will receive the new release at no additional charge.

Secondly, TransEDA is introducing VN-Check, a parametric design rule checker.

"VN-Check catches bugs before anything else can even see them," said Tom Borgstrom, TransEDA vice president of marketing. "It's the ultimate in flexibility for both individual designers and corporate CAD groups. Simple 'linting' tools with a static rule set just don't offer the flexibility and control needed for regular use."

TransEDA found benefits in taking up Java, as many others are similarly reporting. The VN-Check custom rule generator calls for rules to be specified using Java and that increases the sophistication of the tool's error-handling. VN-Check for Verilog is available now in a stand-alone configuration. It will be fully integrated into Verification Navigator this month with support for Verilog and VHDL.

List price for VN-Check starts at $15,000 for a single language when bundled with the base configuration of Verification Navigator, and at $20,000 as a stand-alone product. List price for VN-Check CRG is $45,000. Current Verification Navigator customers will be able to purchase VN-Check in the stand-alone configuration at the bundled price for a limited time.

And finally, today TransEDA reports the publication of the Verification Methodology Manual (VMM). TransEDA is wisely using the name recognition of the Reuse Methodology Manual (RMM) written by Michael Keating of Synopsys Inc. and Pierre Bricaud of Mentor Graphics.

In fact, Bricaud of Mentor is endorsing the book. "The VMM is a significant new book in system-on-a-chip verification and testbench code coverage," he said. "It is a natural follow-up to reading the RMM." The authors of the VMM are David Dempster, founder of Teamwork International, a design consultancy and management training company, and Michael Stuart, TransEDA co-founder and director of customer and technical support. The VMM is available immediately for $65 from the TechOnLine Store at www.techonline.com.

Prolific Rolls 'Liquid Libraries' Software

Prolific Inc., Newark, Calif., today introduces the next generation of its software for generating and migrating standard-cell libraries. Prolific says its new Liquid Libraries tool integrates the creation of standard-cell libraries--building blocks of digital ICs--into the mainstream EDA flow. Design-specific standard cells can be created on-the-fly during synthesis/place-and-route phase. In the past, semiconductor companies have relied on general-purpose standard-cell libraries created independently from the designs that use them.

Prolific has pulled the library creation process into the mainstream physical design flow, said Paul de Dood, president and chief executive officer of Prolific. Existing libraries can be augmented as needed, or the entire library can be built automatically. Prolific also announced partnerships with Cadence Design Systems, Circuit Semantics, Magma Design Automation, Monterey Design Systems, Numerical Technologies, Sapphire Design Automation, Silicon Metrics, Silicon Perspective, Ultima Interconnect Technology and Z-Circuit Automation, in support of the Liquid Library technology.

"By giving our synthesis flow the ability to request the creation of design-specific cells on-the-fly," said Jeff Roane, vice president of SP&R marketing at Cadence, "we ensure that the design effort focuses on the cells that are actually used, and we custom tailor cells to fit the design."

C Level Rolls Out Compiler, and Simulator

On the system-level design front, San Jose-based C Level Design Inc. introduced two products in the lead-up to DAC: System Compiler 4.0 and CSim 2.0. The compiler has a new option called CycleC that supports a cycle-accurate coding style that C Level says increases verification performance on 1 million-plus gate designs by 250 to 400 times. That comparison is against native-compiled Verilog. Performance is said to be up to 1,500 times faster than native-compiled Verilog that uses programming language interface test benches. The CycleC design style is based on native ANSI C/C++ and does not require the use of a C++ class library.

On the other hand, the new Csim 2.0 tool adds features for C/C++ class library-based design and verification. It's now integrated with the ModelSim simulator from Mentor Graphics Inc. and the Scirocco VHDL simulator from Synopsys Inc. to support co-simulation of C/C++ designs with legacy HDL. Also new is simulation support for Synopsys' SystemC 1.0 class library.